`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/10/08 21:18:07
// Design Name: 
// Module Name: RAM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.02 - File Renamed
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module DM(
    input clk,
    input we,
    input [9:0] addr,
    input [31:0] data_r,  
    output [31:0] data_w 
    );
    
    reg [31:0] rf[1023:0];
    //0 - 0x2fff: .data
    //0x3000

    assign data_r = rf[addr];

    always @(posedge clk) begin
        if (we) 
            rf[addr] <= data_w;
    end
endmodule
